[self-interest] Re: Self hardware

Jecel Assumpcao Jr jecel at lsi.usp.br
Fri Aug 6 18:37:42 UTC 1999

Gilad Bracha wrote:
> At 03:46 PM 7/23/99 , Jecel Assumpcao Jr wrote:
> >[merlin 6]
> Please do post any details you can (without, of course, disclosing anything
> proprietary).

Don't worry about that - all information about it will be
available on the web under two licenses (see the end of the
page on http://www.lsi.usp.br/~jecel/merlin4.7 for an idea of
what they will be like).

Merlin 6 will be a small computer/keyboard combination (like
the Commodore 64) and will include a pointing device like the
"hula pointer" used in some notebooks.

Along the back will be the digital ports:

 - USB
 - Firewire (three connectors)
 - Fast Ethernet
 - VGA out (not really digital, but...)

and on the side we have the analog ports:

 - video out (NTSC and PAL)
 - video in (NTSC and PAL)
 - sound out (mono)
 - sound in (mono)
 - telephone (V.34 modem initially)

There is also a power cord and space for an optional battery.
It is powered by a Xilinx Virtex XCV 300-6 field programmable
gate array and also a Xilinx Spartan FPGA. It includes 32MB of
100 Mhz SDRAM, 640 KB of 10 ns SRAM (for the caches) and a
2 MB Flash memory. The rest of the circuit is composed of small
interface chips. A DIMM socket allows expansion of the SDRAM.

The cache memory is linked to the FPGA over an 80 bit wide bus
(including both tag and data information). It is divided into
four regions: the data cache, the microcode cache, the PICs
and the translator. The internal architecture of the CPU is
a four issue MOVE (or TTA. See http://cardit.et.tudelft.nl/MOVE/)
with four moves on each 64 bit instruction word. This is the
"microcode" for the machine and is only stored in the microcode
cache and the translator area. The externally visible machine
code is simply Self bytecodes (but could be Java or Smalltalk
bytecodes) and that is what is stored in main memory.

The microcode cache and the "loop coprocessors" (for multimedia.
I hadn't mentioned them yet...) are rather complicated, so I'll
post a link here as soon as I finish the web pages explaining
them. I hope to cycle the CPU at 100 MHz even though I will be
using the slowest speed grade (the other cost too much).

The Flash memory stores the bits for programming both FPGAs and
also the system software. It includes two banks of programming,
selectable with a strap. So you can use the machine to call up
its own design, change it and save it to bank B in the Flash.
Then you open up the machine (I feel that if you are not up to
messing inside the machine, you shouldn't be redesigning it!)
and change the strap to it tries to load from bank B after a
reset. If that doesn't work, you move the strap back to A and
boot normally into Self/R to change the design again to try to
fix the problem. If you end up ruining both banks and can't
boot the machine anymore, then set the strap to a third position
and connect a cable to either another Merlin 6 or a PC with the
right software and you can wipe the Flash clean and load a
working design into it.

I think this is about as "open" as hardware will ever get and
will be a great learning experience for the new generations
that didn't get to build stuff from TTLs. What do you think?

-- Jecel
P.S.: I got the site running over a 33kbps
link, but the pages there are just placeholders until I can
write something better.

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